DUMP=DUMP
LONG=NONE
TOP=tb_MACArray
DEBUG_COMP_OPTS += -assert svaext
LINT_COMP_OPTS  += +lint=all,noVCDE,noNS
#TOP=pe_array
TB_VLOG_F  = -f ./all.vc
VLOG_COMP_OPTS += -full64  -LDFLAGS -Wl,--no-as-needed  -lca -kdb +vcd+vcdpluson -Mupdate
VLOG_COMP_OPTS += -sverilog -v2k_generate
VLOG_COMP_OPTS += -timescale=1ps/1ps
VLOG_COMP_OPTS += +define+VCS
VLOG_COMP_OPTS += $(TB_VLOG_F)
VLOG_COMP_OPTS += $(DEBUG_COMP_OPTS)
VLOG_COMP_OPTS += $(LINT_COMP_OPTS)
VLOG_COMP_OPTS += $(UVM_COMP_OPTS)
VLOG_COMP_OPTS += $(RAL_COMP_OPTS)
VLOG_COMP_OPTS += +incdir+./+incdir+../

VSIM_OPTS += -LDFLAGS -Wl,--no-as-needed  -lca -kdb

TB_TOP_MODEL_NAME  = tb_MACArray
LICENSE_OPTS    += +error+1000
LINT_COMP_OPTS  += +lint=all,noVCDE,noNS
DEBUG_COMP_OPTS += 
#DEBUG_ELAB_OPTS += -debug_access+pp+drivers
DEBUG_ELAB_OPTS += -debug_pp 

ELAB_OPTS += -full64 -lca -kdb -debug_pp +vcd+vcdpluson -Mupdate
ELAB_OPTS += $(LICENSE_OPTS)
ELAB_OPTS += $(DEBUG_ELAB_OPTS)
ELAB_OPTS += $(UVM_ELAB_OPTS)
ELAB_OPTS += $(COV_ELAB_OPTS)
ELAB_OPTS += $(OPT_CONFIG_F)
ELAB_OPTS += $(XILINX_CORE_ELAB_OPTS)
ELAB_OPTS += +lint=TFIPC-L

RUN_OPTS +=	$(LICENSE_OPTS)
RUN_OPTS +=	$(DEBUG_RUN_OPTS)
RUN_OPTS += $(RAL_RUN_OPTS)
RUN_OPTS += $(COV_RUN_OPTS)
RUN_OPTS += +UVM_TESTNAME=base_test
RUN_OPTS +=	+vpdfileswitchsize+3000
RUN_OPTS +=	+ntb_random_seed=$(SEED)
RUN_OPTS +=	+notimingcheck

CFLAG	   = -D_FILE_OFFSET_BITS=64 -D_LARGE_FILE -g
##C_HOME = ../test_pe
VERDI_PATH = /home/xlg/Synosys2018/verdi/Verdi_O-2018.09-SP2



default:
	##vcs -full64 -cpp g++-4.8 -cc gcc-4.8  -f all.vc  -top  tb_MACArray   ${VSIM_OPTS}  $(ELAB_OPTS) $(OBJ_LIST)     -l elab.log 
	vcs  $(VLOG_COMP_OPTS) -full64   -f all.vc  -top  tb_MACArray -P  $(VERDI_PATH)/share/PLI/VCS/LINUX64/novas.tab   $(VERDI_PATH)/share/PLI/VCS/LINUX64/pli.a  ${VSIM_OPTS}  $(ELAB_OPTS) $(OBJ_LIST)     -l elab.log 
	./simv $(RUN_OPTS)   -l run.log		
	@echo "sim end   time is:" `date '+%Y-%m-%d %H:%M:%S'` >> time.log


com:
	@echo "sim start time is:" `date '+%Y-%m-%d %H:%M:%S'` >> time.log
	rm -rf mywork
	mkdir -p mywork
	vlogan -work mywork ${VLOG_COMP_OPTS}     -l comp_vlog.log
	vcs -full64 -cpp g++-4.8 -cc gcc-4.8   ${VSIM_OPTS}  mywork.$(TB_TOP_MODEL_NAME) $(ELAB_OPTS) $(OBJ_LIST)     -l elab.log   -P  $(VERDI_PATH)/share/PLI/VCS/LINUX64/novas.tab   $(VERDI_PATH)/share/PLI/VCS/LINUX64/pli.a

sim:
	./simv $(RUN_OPTS)   -l run.log		
	@echo "sim end   time is:" `date '+%Y-%m-%d %H:%M:%S'` >> time.log



verdi:
	verdi -sv -f all.vc &

clean:
	rm -rf novas.conf  novas.rc  verdiLog  simv*  csrc   *.log verdiLog   vc_hdrs.h  tb.sv~  ucli.key mywork  *.vf *.vpd *.fsdb 
	rm -rf 1* 2* 3* 4* 5* 6* 7* 8* 9*  DVEfiles 


emacs:
	cp  ../src/DDC_Core/DDC_Core.v  ./
	emacs   --batch   tb.sv             -f verilog-auto     -f save-buffer
	rm DDC_Core.v 

grep:
	grep CASE  run*.log   > result

